Prototype chip reaches record transistor density with stacked silicon layers

A prototype chip measuring 10 by 15 millimetres contains nearly 100 billion transistors, almost twice the number in the previous state-of-the-art chip. The design stacks two silicon layers to achieve the density increase. The company stated the chip will deliver 70 per cent higher energy efficiency and 50 per cent higher performance than current leading chips.

It expects the technology to appear in commercial devices within 10 years.

Size labels such as "0.7 nanometre" now serve mainly as marketing terms rather than physical measurements. The new process bonds two silicon layers while forming all required electrical connections and maintaining heat dissipation suitable for mass production. The company described the method as the first to scale transistors along the vertical, or Z, axis.