University of Illinois Team Stacks Silicon Circuits at 200 Degrees Celsius

Researchers at the University of Illinois Urbana-Champaign stacked three layers of high-performance silicon circuits on a single 200-mm wafer using bonding temperatures no higher than 200 degrees Celsius. Each layer contained 625 transistors, and the devices recorded yields between 98% and 100% while matching the performance of conventional transistors made at much higher temperatures.

The team transferred ultrathin single-crystalline silicon nanomembranes onto completed circuit layers, then connected the layers with vertical metal links to form three-dimensional logic circuits and static random-access memory cells.

They also redesigned the transistors as junctionless devices that could be prepared before stacking began. Qing Cao, associate professor of materials science and engineering at the university, said the approach replaces a single-plane layout with vertical integration. "Take something as simple as static random-access memory, which is universal in CPUs and GPUs.

Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. " Standard silicon processing reaches temperatures near 1,000 degrees Celsius, but once the first layer and its metal wiring are finished, later layers must stay below roughly 400 degrees Celsius to protect existing structures.

The Illinois process stays at or below 200 degrees Celsius, satisfying the thermal limit for monolithic three-dimensional integration. Cao said vertical stacking is already appearing in specialized AI hardware, yet monolithic integration remains the step that realizes the full potential of three-dimensional chips.

"For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance," he said.

The researchers demonstrated that the method is scalable. "But most we've shown that this process is scalable. You can keep stacking layers beyond the three we demonstrated," Cao said. Most existing three-dimensional chip technologies bond separately manufactured wafers, which produces larger connections and lower density.

The Illinois approach builds each circuit layer directly on the previous one, allowing denser vertical links and tighter alignment. The study appeared in the journal Nature. The team is now working to move the process into an industrial semiconductor foundry, with support from IBM, Intel, and TSMC.